1. Field of the Invention
This invention concerns a driving circuit, such as a driving circuit suitable for driving the word lines, etc., in a dynamic RAM (Random Access Memory).
2. Description of the Prior Art
In conventional techniques of dynamic RAM design, the most important point is to increase the difference .DELTA.V between the bit line voltage representing information "1" and that representing information "0." Assume that the bit line capacitance is C.sub.B, the cell capacitance is C.sub.S, the cell voltage with information "1" stored is V.sub.H, and the cell voltage with information "0" stored is V.sub.L, .DELTA.V can then be represented as ##EQU1##
As can be seen from the above equation, one way to increase .DELTA.V is to reduce the ratio C.sub.B /C.sub.S, which depends on the memory cell structure and the number of memory cells coupled to a single bit line. Another way is to increase the value of said (V.sub.H -V.sub.L) in the circuit. However, V.sub.L (cell voltage for stored information "0") is usually 0V, while V.sub.H (cell voltage for stored information "1") depends on the voltage V.sub.WL when the word lines are open. Assume that the word line voltage V.sub.WL is set as power supply voltage V.sub.DD, and the threshold voltage of the transfer gate of the memory cell is V.sub.T (WL), then EQU V.sub.H =V.sub.DD -V.sub.T (WL)
Hence, V.sub.H is lower than power supply voltage V.sub.DD by an amount equal to the threshold voltage (this, of course, decreases said value of (V.sub.H -V.sub.L), making it impossible to increase the bit line voltage difference .DELTA.V). In order to solve this problem, various techniques related to circuits have been proposed to raise the word line voltage V.sub.WL higher than the power supply voltage V.sub.DD (i.e., V.sub.WL &gt;V.sub.DD +V.sub.T (WL)).
An increase in the said bit line voltage difference .DELTA.V not only can increase the operating margin of the dynamic RAM, it is also effective in providing an improvement against so-called soft errors caused by -particles, etc.
In the following, we will discuss the problems in an example of the conventional circuit technique for raising said word line voltage V.sub.WL to a level above the power supply voltage V.sub.DD, with reference to FIGS. 12-17.
First of all, FIG. 14 is a schematic block diagram of the circuit from RAS (Row Address Strobe) of, for example, a 1 M dynamic RAM to various word lines (for example, 512 lines). Its major operation mode can be explained as follows.
As shown in FIG. 14, a clock signal (RL21) generated by RAS clock generator (1), for generating the operating clock of the RAS system upon the arrival of RAS, controls address buffer (2) and booster circuit portion (4). At the falling edge of RAS, address (A.sub.0 -A.sub.8) is fetched by clock (RL21 into address buffer (2); the outputs of address buffer (2) (RA0, RA0-RA7, RA7) are predecoded by predecoder (3). Among the outputs from the predecoder, the upper bits (RF4)-(RF15), RA8, and RA8 are sent to X decoder portion (5); the lower bits (RF0)-(RF3) are sent to booster circuit portion (4), respectively, and used for control. At X decoder portion (5), each decoder is selected therewithin by the above RF4-RF15, RA8, and RA8. Finally, with the aid of four clocks RXH0-RXH3 formed by booster circuit portion (4) and connected to word line driving circuit (6), one word line out of the 512 word lines (WL0-WL511) is selected.
FIGS. 15 and 16 illustrate each connection relationship as well as operation of word line driving circuit portion (6), X decoder portion (5), and booster circuit portion (4) in FIG. 14.
As shown in FIG. 15, X decoder portion (5) is made of 4-input AND circuits, with a total number of 128 (4.times.4.times.4.times.2=128) said 4-input AND circuits (5a) being made of the various combinations of inputs RF4-RF7, RF8-RF11, RF12-RF15, RA8 and RA8, respectively (only one 4-input AND circuit (5a) is shown in FIG. 15 to simplify the explanation). The output of each said 4-input AND circuit (5a) is connected to one of the inputs of four 2-input AND circuits (6a) in word line driving circuit portion (6), respectively. The other inputs of these AND circuits (6a) are connected to RXH0-RXH3, output signals from booster circuit portion (4) as shown in FIG. 14. The output of each of said four 2-input AND circuits (6a) is connected to four word lines (such as WL0-WL3). That is, in the circuit shown in FIG. 15, each circuit group contains one 4-input AND circuit (5a) and four 2-input AND circuits (6a ); for the said 4-input AND circuit (5a), there are 128 combinations of inputs; each of the 128 circuits has four word lines (such as WL0-WL3); hence, there are in total 512 word lines.
Selection of each of the word lines (WL0-WL511) in FIG. 15 is performed as follows. For RF4-RF15, as explained above, depending on the predecoded address signal (A0-A7), among the four signals RF4-RF7, only one is set at level "1"; similarly among RF8-RF11, only one is set at level "1"; among RF12-RF15, only one is set at level "1"; and among RA8 and RA8, only one is set at level "1". On the other hand, along the four signals RXH0-RHX3 at booster circuit portion (4), only one is set at level "1"; hence, the total number of combinations is 128.times.4=512 (cases), and it is possible to select one out of 512 word lines (WL0-WL511).
As shown in FIG. 16, booster circuit (4) consists of four identical circuit blocks (4a) (the internal circuit of which will be explained later with reference to FIG. 12). Circuit blocks (4a) have said predecoded signals RF0-RF3 and signal RF21 from RAS clock generator (1) as their inputs, respectively. Circuit blocks (4a) output signals RXH0-RXH3, respectively. Signal RL21 connected to said booster circuit portion (4) is called a delayed function enable signal. Signal RL21 is used for determining the output timing of signals RXH0-RHX3. The time point determined by the output of said X decoder portion (5) (5a) is used as its timing.
In the following description, with reference to FIG. 12, an example of the internal circuits of word driving circuit portion (6), booster circuit portion (4) and X decoder portion (5) will be presented together with an explanation of their operation. In order to facilitate the explanation, FIG. 12 only depicts a part of the major configurations of the internal circuits.
With regard to X decoder portion (5) shown in FIG. 12, four N-channel MOS transistors Q2-Q5 are connected to each other with the drains of respective transistors being connected to the source of the adjacent transistor. The source of transistor Q5 is connected to ground V.sub.SS. The drain of transistor Q2 is connected to the drain of P-channel MOS transistor Q1. In addition, the source of transistor Q1 is connected to power supply V.sub.DD. The gate of transistor Q1 is connected to precharge signal PC. Gates of transistors Q2-Q5 are connected to said signal inputs RF4-RF15, RA8 and RA8, respectively (i.e., said transistors Q2-Q5 form said 4-input AND circuit 5a).
In addition, the drain of P-channel MOS transistor Q1 (or the drain of N-channel MOS transistor Q2) is connected to the drain of P-channel MOS transistor Q6 and the gates of P-channel MOS transistor Q7 and N-channel MOS transistors Q8 and Q11, respectively. The source of transistor Q6 and the source of transistor Q7 are connected to power supply V.sub.DD, respectively. The source of transistor Q8 is connected to ground V.sub.SS ; the drains of transistors Q7 and Q8 are connected with each other; their drains are connected to the gate of transistor Q6 and the drain of N-channel MOS transistor Q9 in word line driving circuit portion (6) to be described later, respectively.
In FIG. 15, in order to facilitate explanation, the explanation is omitted for the portions corresponding to the circuit configurations of said transistors Q6, Q7, and Q8.
Now, with regard to word line driving circuit portion (6), the 2-input AND circuit (6a) is made of two N-channel MOS transistors Q10 and Q11. That is, the source of transistor Q10 and the drain of transistor Q11 are connected to each other; the drain of transistor Q10 is connected to outputs RXH0-RXH3 of booster circuit portion (4); the source of transistor Q11 is connected to ground VSS The gate of transistor Q9 is connected to power supply VDD; its source is connected to the gate of transistor Q10. The source of transistor Q10 (or the drain of transistor Q11) is connected to word lines WL0-WL511. The explanation is omitted for the portions corresponding to the circuit configurations of said transistor Q9 and Q10 in FIG. 15 to simplify the explanation.
Explanation will follow with regard to FIG. 12 for one circuit block (4a) of the booster circuit portion (4) in FIG. 16. Clock RL21 and RF0-RF3 are connected to the inputs of 2-input NAND gate (7). Its output is connected via inverter (8) to the drain of N-channel MOS transistor Q12, and via three inverters (9) (in this example, the 3 inverters form a delay circuit) and capacitor (Cl) to the drain of transistor Q10. Besides, the gate of transistor Q12 is connected to power supply V.sub.DD, and its source is connected to the drain of transistor Q10.
In order to produce output clock signals RXH0-RXH3 in the booster circuit portion (4), node (D) is first charged to voltage V.sub.DD -V.sub.T, which is lower than the power supply voltage by V.sub.T, the threshold voltage of N-channel MOS transistor Q12, with node (C) being at level "L". The voltage at node (D) is increased due to capacitive coupling via capacitor Cl with a time difference caused by inverters (9). RF0-RF3 and RL21 enable) play the role of controlling timing of word line driving circuit portion (6) to be explained later. They also play the role of a decoder by selecting one out of the said four word lines (one out of WL0-WL3 in the example shown in FIG. 15).
In the following, an example with specific values of voltage levels for the major operation process of FIG. 12 will be described. First, in the precharge state, the precharge signal PC at the input of the gate of P-channel MOS transistor Q1 becomes level "0"; the partially decoded row address signals (RF4-RF15, RA8, and RA8 in FIG. 14) set all the gates of N-channel MOS transistors (Q2)-(Q5) to level "0." Hence, transistors Q2-Q5 are all in the OFF state, and transistor Q1 is in the ON state, such that the voltage at the node (E) increases to 5 V (V.sub.DD).
P-channel MOS transistor Q6 latches said node (E) at the 5 V state. Node (E) is kept at 5 V even when the precharge signal PC disappears (i.e., even when precharge signal PC becomes level "1" and transistor Q1 is turned OFF, transistor 6 is in the ON state due to the level "0" output of the inverter made of transistors Q7 and Q8; hence, node (E) is maintained at 5 V). In this case, nodes (F) and (G) are at 0 V (V.sub.SS), and all of the word lines (WL0-WL511) are also at 0 V, since N-channel MOS transistor Q11 is in the ON state.
Then, when the operation state occurs, the partially decoded row address signals (RF4-RF15, RA8, and RA8) set level "1" for all the gates of transistors Q2-Q5; hence, they all turn to the ON state. Therefore, node (E) is charged to 5 V contrary to the above operation; furthermore, because of transistor Q9 (this transistor Q9 is always in the ON state because its gate is connected to the power supply voltage V.sub.DD), the voltage at node (G) falls by the threshold voltage V.sub.T (1 V) of transistor Q9 to be charged to 4 V. After charging is finished, transistor Q9 is turned OFF; hence, node (G) is in a floating state.
By raising one of RXH0-RXH3 from 0 V to 5 V, with node (G) being charged to 4 V, node (G) is so-called, self-booted (self step-up) by transistor Q10 to be charged to about 8 V. With regard to the said self-boot phenomenon, when node (G) is at 4 V, and RXH0-RXH3 as well as each word line (WL0-WL511) is at 0 V, transistor Q10 is ON; equivalently, node (G) may be regarded as being connected to RXH0-RXH3 and word lines (WL0-WL511) with a capacitor therebetween. The capacitor has a capacitance equal to the gate capacitance of transistor Q10 in the ON state. In this case, when one of RXH0-RXH3 is changed from 0 V to 5 V, the voltage at node (G) increases due to the capacitance of the said capacitor (the gate capacitance of transistor Q10). Ideally, it should be increased by 5 V. However, in the actual situation, due to the charge share with the self-capacitance of node (G) (wire capacitance of node (G), the capacitance of diffusion layer of transistor Q6, etc.), the voltage increase cannot reach 5 V and is usually about 3-4 V.
As explained above, as node (G) is boosted to a voltage of about 8 V, the 5 V voltage can be transmitted from RXH0-RXH3 to the word line (for example, WL0) with the aid of transistor Q10. When data are refreshed (rewritten) in the dynamic RAM, word line boosting circuit portion (4) boosts RXH0-RXH3 from 5 V to 8 V, and boosts node (G) to about 12 V; hence, the worked line (for example, WL0) is further charged to 8 V. Besides, as explained above, in X decoder portion (5) in FIG. 14, each decoder is connected to four word lines (such as, WL0-WL3). Among these lines, only one (for example, WL0) is finally selected through word line driving circuit portion (4) (see FIGS. 14-16).
Now, with reference to FIGS. 13 and 14, described below is the major operation before a high-voltage output V.sub.PP (for example, 8 V) from booster circuit portion (4) is output to the word line selected by the input signal of the RAS system shown in FIG. 14 as described above.
First, with RAS being at level "0" at time t1, signal RL21 which is provided by RAS clock generator (1) becomes level "1" at time t.sub.2 and is entered into address buffer (2). Due to signal RL21, at time t.sub.3, row address inputs A0-A8 are taken into address buffer (2); at the same time, output signals RA0, RA0-RA7, and RA7 from address buffer (2) are taken into predecoder (3); and RA8 and RA8 are each taken into X decoder portion (5).
Then at time t.sub.4, signals RF0-RF3 predecoded at predecoder (3) ar taken into booster circuit portion (4), while RF4-RF15 are taken into X decoder portion (5). At time t.sub.5, output signals RXHO-RXH3 from booster circuit portion (4) and signals RF4-RF15, RA8, and RA8 input into the X decoder (5) select, as described above, a work line (for example, WL0) which acquires a high-voltage output V.sub.PP (for example, 8 V) at time t.sub.6 through work line driving circuit portion (6).
As explained above, in the dynamic RAM, X decoder portion (5), word line driving circuit portion (6), and booster circuit portion (4) form the driving circuit. As explained above with reference in FIG. 12, in the work line driving circuit portion (6) within the said driving circuit, because N-channel MOS transistor Q10 has to transfer the levels (voltages) of RXH0-RXH3 by self-boot operation, the timing of the operation of node (E) and RXH0-RXH3 must be controlled. That is, the signals must be controlled to ensure the following relationship: after node (E) reaches level "0" (0 V) and node (G) reaches V.sub.DD -V.sub.T (about 4 V) which is lower than the power supply voltage by threshold voltage V.sub.T of transistor Q9, RXH0-RXH3 rise. In this case, the necessity for performing timing control (or, control of sequence) in the said self-boot (self-step-up) operation is as follows: when the voltages at nodes (F) and (G) are lower than V.sub.DD -V.sub.T, i.e., V.sub.DD -V.sub.T &gt;V.sub.F (voltage of node (F)), a prescribed voltage (for example, 5 V) enters transistor Q10 due to RXH0-RXH3; an attempt to raise node (G) by coupling of the gate capacitance of transistor Q9 only results in the electric charge escaping to node (F) through the channel of transistor Q9.
As explained above, if signals RXH0-RXH3 are not raised in a timing after transistor Q9 is pinched off (i.e., the state in which the charge cannot leak from node (G) to (F) with the voltage of node (G) being V.sub.DD -V.sub.T (about 4 V), the self-boot operation due to the gate capacitance of transistor Q10 could not be performed. As explained above with reference to FIGS. 13 and 14, because the timing of output signals RXH0-RXH3 from word line driving circuit portion (4) has to be controlled sequentially according to row address inputs (A0-A8) taken due to signals of RAS and RL21, to provide a high-voltage output V.sub.PP (for example, 8 V) to the selected word line (for example, WL0) takes a very long time. Actually, as shown in FIG. 17, after row address input (A0-A8) is taken, it takes about 13 ns before one of the word lines (WL0-WL511) reaches 5 V. (As a matter of fact, if the margin of the power supply voltage V.sub.DD and the temperature margin are taken into consideration, a longer time will be needed. This is a serious problem in realizing high-speed operation of a dynamic RAM, etc.
The purpose of this invention is to provide a type of driving circuit that can output driving signals with a predetermined voltage in a short time to output lines, such as word lines or the like, in a dynamic RAM.